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GTC ON-DEMAND

Developer - Algorithms
Presentation
Media
Gate-Level Simulation with GP-GPUs
Speakers:
Debapriya Chatterjee
- University of Michigan
Abstract:
This poster describes my research work on how to leverage the GP-GPU execution parallelism to achieve high performance in the time consuming problem of gate-level simulation of digital hardware designs.
 
Topics:
Developer - Algorithms
Type:
Poster
Event:
GTC Silicon Valley
Year:
2010
Session ID:
P10A16
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General Interest
Presentation
Media
Gate-Level Simulation with GP-GPUs
Speakers:
Debapriya Chatterjee
- University of Michigan
Abstract:
Logic simulation is a critical component of the digital design tool flow. It is used from high-level descriptions down to gate-level to validate several aspects of the design, particularly functional correctness. Despite development houses investing vast resources in the simulation task it is still far from achieving the performance demands of validating complex modern designs at gate-level. We developed a GP-GPU accelerated gate-level simulator using NVIDIA CUDA. We leverage novel algorithms for circuit netlist partitioning and found that our experimental prototype could handle large, industrial scale designs comprised of millions of gates while delivering 13x speedup on average over a typical commercial simulator.
 
Topics:
General Interest
Type:
Talk
Event:
GTC Silicon Valley
Year:
2010
Session ID:
P10A16
Streaming:
Download:
Share: