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GTC ON-DEMAND

Algorithms & Numerical Techniques
Presentation
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High Performance Hierarchical Matrix-Vector Multiplication using Hardware Accelerators
Abstract:
We present a high performance hierarchical matrix vector multiplication using hardware accelerators. By properly mapping the tree structures to the GPU and overlapping the phases of the computation using streams, we greatly outperform the CPU implementations and achieve up to 80% of the sustained bandwidth of the GPU.
 
Topics:
Algorithms & Numerical Techniques, HPC and Supercomputing
Type:
Poster
Event:
GTC Silicon Valley
Year:
2016
Session ID:
P6140
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