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GTC ON-DEMAND

Developer - Algorithms
Presentation
Media
Parallelizing FPGA Technology Mapping using GPUs
Speakers:
Doris Chen
- University of Toronto
Abstract:
FPGA technology mapping is an algorithm that is heavily data parallel, but contains many features that make it unattractive for GPU implementation. The algorithm uses data in irregular ways since it is a graph-based algorithm. It also makes heavy use of constructs like recursion which is not supported by GPU hardware. In this paper, we take a state-of-the-art FPGA technology mapping algorithm within Berkeley's ABC package and attempt to parallelize it on a GPU. We show that runtime gains of 3.1x are achievable while maintaining identical quality as demonstrated by running these netlists through Altera's Quartus II place-and-route tool.
 
Topics:
Developer - Algorithms
Type:
Talk
Event:
GTC Silicon Valley
Year:
2010
Session ID:
S102068
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